• COMM. CONTROLLER: Fastcom F-Core
• INTERFACE: RS232
• CONNECTOR CONFIGURATION: Cable assembly (2 ft.) – HDDB62 plug to two DB25 plugs
• BUS INTERFACE: PCI Version 2.3
• BAUD RANGE: Using the user independent programmable clock generator in conjunction with the baud rate register, virtually any baud rate from 1 bps to 1 Mbit/s can be attained.
  • Maximum data rates are estimates. They are greatly affected by a number of different factors. See the data rates section of the manual for more details. This is possible as long as the operating parameters are within reason. If you have any question about whether the card can meet your needs, please contact Technical Support.
• POWER REQUIREMENTS: +5V @ 450mA (typical)
• ENVIRONMENT:
  • Operating Temperature Range: 0 to 70 C
  • Humidity: 0 to 90% (non-condensing)
• DIMENSIONS:
  • Half-length full-height
  • Height: 4.2″ (107 mm)
  • Length: 4.7″ (119.91 mm)
  • Weight: .2 lbs (90.719 g)

• Never Obsolete
• Customizable Firmware: The firmware for our FSCC and SuperFSCC product lines is fully-customizable. If you have a feature requirement you do not see listed, please contact us about modifying our firmware to meet your specific needs.
• High speed: Up to 1 Mbits/s
• Drivers: RS232
• True-Async mode. Each port can be set to use the on-board 16C950 UARTs and can be used as a standard serial (COM) port.
• Automatic RS-485 handling
• Transmit and Receive status LED’s for each port.
• On board RS-485 termination network for each receive signal pair
• Two independent full duplex serial channels
  • Data clocking mechanism independently selectable per channel per direction
    • Externally generated Rx and Tx clocks
    • Internally generated Rx and Tx clocks
    • On chip DPLL clock recovery
    • Independent baud rate generators
• FIFOs
  • RxFIFO = 8KB per port (non-uart modes)
  • TxFIFO = 4KB per port (non-uart modes)
  • Programmable interrupt trigger levels (watermark)
• Data protocols
  • HDLC/SDLC
    • The FSCC and SuperFSCC families of cards fully supports the HDLC framing convention. It does not support automatically decoding of the SDLC control fields. If control bytes are present in received frames they will be passed to the user as if they were part of the info field. If control bytes are required to be transmitted they will have to be generated by the user and written as if they were data.
    • Automatic flag detection and transmission
    • General frame format: 0x7e,info,CRC,CRC,[CRC,CRC,]0x7e
    • Frame format with maskable address enabled: 0x7e,address,[address,]info,CRC,CRC,[CRC,CRC,]0x7e
    • Zero insertion/deletion
    • One insertion/deletion
    • Shared flag mode: opening flag and closing flag of back-to-back frames can use the same flag.
    • Error detection (abort, overrun, underrun, CRC error, too long/short frame)
    • Can use CRC8, CRC-CCITT, or CRC32
  • Arbitrary Sync Sequence (Fastcom®: X-Sync)
    • Any begin/end frame sync sequence of up to 4 bytes
    • Frame format: SYN1,[SYN2,SYN3,SYN4,]info,[CRC,CRC, CRC,CRC,][TCR1,TCR2,TCR3,TCR4]
    • Maskable: can select all or parts of the sync sequence to be a sync match
    • Termination sequence detection up to 4 bytes (maskable)
    • Shared flag mode: opening flag and closing flag of back-to-back frames can use the same flag.
    • Error detection
    • Can use any of the available CRC methods
  • Transparent Mode
    • Fully bit transparent (no framing or bit manipulation)
    • Can synchronize using selectable frame sync signals
• Data encoding schemes:
  • NRZ, NRZI, FM0/FM1, Manchester
• Selectable frame sync signals
  • Pulse width of one clock at first bit of data
  • Pulse width of one clock at last bit of data
  • Pulse width of the entire frame
  • Optionally insert a variable number of clock cycles between data and FSS
  • Selectable polarity
• Optional data flow control using modem control lines (RTS, CTS)
• Programmable 8-bit preamble and postamble with selectable repetition rate (1 to 255 repetitions)
• Data can be oriented as selectable MSB first or LSB first
• Interframe time fill: idle as repetitive 1’s, flags, or sync sequences
• CRC Support
  • Automatic handling in the transmit/receive direction
  • CRC-CCITT (also known as CRC16-ITU) (HDLC), CRC32 (HDLC), CRC16, CRC8 (HDLC)
  • Transparent CRC option
  • Reset as 0’s / 1’s
• Continuous transmission of 1 to 4096 bytes
• Selectable data rates
  • Synchronous (internally clocked) data rates up to 1 Mbit/s
  • Synchronous (externally clocked) data rates up to 1 Mbit/s
  • Asynchronous (DPLL clock recovery) data rates up to 1 Mbits/s
  • These data rates are the maximum guaranteed rates. While it is possible to clock the 232 transceiver chips at faster speeds, they are greatly affected by a number of different factors. See the Baud Rates section of the manual for more details.
• Data and clock inversion
• Interruptible hardware timer
• Transmit a single frame on the expiration of the hardware timer
• Included Libraries:
  • C
  • C++
  • .NET
  • Python
  • Network Analyzer
  • Wireshark
• Cable, documentation, and software drivers included
• Designed and manufactured by COMMTECH, INC. Wichita, Kansas, USA

• Drivers are available for:
  • Windows XP through Windows 10, 32 and 64 bit
  • Linux 2.6.16-3.X
• Included Libraries:
  • C
  • C++
  • .NET
  • Python
  • Network Analyzer
  • Wireshark

Click here for Fastcom: FSCC-232 drivers. Click here for the Fastcom: FSCC-232 product manual.